1) Field of the Invention
The present invention relates to a technology for generating validation items to create an input/output sequence called a test pattern.
2) Description of the Related Art
Conventionally, a large scale integrated circuit (LSI) design necessitates a validation process to validate a normal operation of the LSI, as well as an improvement in work efficiency by shortening a time for the design. Particularly, the validation process is an indispensable step to maintain high quality of the LSI that requires large scale, advanced function, high speed, and low power consumption.
In the validation process, a series of input/output sequences called a test pattern is created. An input signal is given to the LSI based on the input/output sequence, and it is confirmed whether an output signal from the LSI coincides with an expectation value. With this arrangement, it is possible to validate whether an apparatus is operating as expected. However, there are an enormous number of functional devices within the LSI. With this situation, manual listing of a data flow (i.e., a sequence) between all the functional devices is difficult, and the input/output sequence (i.e., the test pattern) generation is complicated.
Conventionally, there is a method of extracting the input/output sequence from a functional block diagram created by using a predetermined description language. According to the method, the functional block diagram expresses the apparatus to be validated as a functional device and a data flow between the functional devices. A graph is created by replacing the functional devices and the data flow with nodes edges, respectively. Then, one sequence is specified through one path on the graph. As a result, an input/output sequence that is given to the apparatus to be validated can be listed. The conventional method is described in, for example, J. Ryser, M. Glinz, “A Scenario-Based Approach to Validating and Testing Software Systems Using Statecharts”, 12th Intl. Conf. on Software Engineering and their Applications, December 1999.
However, since the functional devices in the LSI operate in parallel based on a parallel execution of the hardware, the conventional method, which can only take a path on the graph into consideration one by one, cannot handle a simultaneous execution of a plurality of sequences. Further, the conventional method does not take into account a resource constraint specific to a hardware such as sharing and exclusive utilization of functional devices in the apparatus to be validated like the LSI.
Therefore, the input/output sequence listed by the conventional method actually includes a non-executable input/output sequence. An attempt to carry out the validation by using the non-executable input/output sequence becomes a failure. Consequently, work time and labor become wasteful, and a design time becomes longer.